Re: [myhdl-list] Re: Problems inferring RAM when it is buried in system

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> The overall message should be that you shouldn't draw too
> many conclusions from conversion/synthesis unless the
> design is clean. Clean meaning that it does something
> useful in simulation.

It can't be stressed enough that the proper flow for logic design with 
MyHDL is the following:

1. MyHDL logic unittest, used here and in steps 2 and 4.
2. Apply unittest to toVerilog logic via cosimulation.
3. toVerilog logic synthesis with your favorite synthesis tool.
4. post synthesis unittest.

If logic changes are required after step 4, all steps should be 
repeated. Note, these can all be automated from the MyHDL unittest.

>
> Note that it is normal and useful for synthesis tools
> to remove "unnecessary" logic, such as anything that
> is not connected to its surroundings.

XST is not that robust of a tool, but in general the cleaner the HDL, 
the less likely you get trouble with any synthesis tool.

Potentially that is another benefit of MyHDL as the Verilog generated 
should be less diverse than you could create from scratch. For example 
RAMs inferred from a list should always produce Verilog that is the same 
structure, leaving less opportunity for a synthesis problem.

Tom