[myhdl-list] Re: Problems inferring RAM when it is buried in system

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Dear Jan and  Tom,
> 
> I have created a simplified, representative mock-up of my system. When 
> this code is processed with myHDL (0.5dev1) and Xilinx ISE WebPACK 
> 7.1.04i, no RAM's are inferred. However, using the same RAM function in 
> a trivial standalone example results in inferred RAM.
> 
> I also noticed a major discrepancy between the HDL Synthesis and the 
> Final Report. Where did those 2048 flip-flops go? A similar discrepancy 
> appears to be in the "real" system too.

George:

I have been able to reproduce your issue.

By now I'm pretty sure that the problem is not related to embedded
code, but to the fact that the design is not clean.

Note that several signals are driven but not used. I have tried
the same with my Ram wrapper code: with the clean version, a
ram gets inferred, but when I disconnect the output register
from its surroundings, I get the same flip-flop inference and
advisor message as you are getting.

For MyHDL, I learn from this that it should issue similar
warning messages as XST about driven but unused signals.
I have added that to the development version.

The overall message should be that you shouldn't draw too
many conclusions from conversion/synthesis unless the
design is clean. Clean meaning that it does something
useful in simulation.

Note that it is normal and useful for synthesis tools
to remove "unnecessary" logic, such as anything that
is not connected to its surroundings.

Jan

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