Re: [myhdl-list] Problems inferring RAM when it is buried in system
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Re: [myhdl-list] Problems inferring RAM when it is buried in system
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From: George P. <ge...@ga...> - 2005-11-30 02:43:37
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Dear Jan and Tom,
I have created a simplified, representative mock-up of my system. When
this code is processed with myHDL (0.5dev1) and Xilinx ISE WebPACK
7.1.04i, no RAM's are inferred. However, using the same RAM function in
a trivial standalone example results in inferred RAM.
I also noticed a major discrepancy between the HDL Synthesis and the
Final Report. Where did those 2048 flip-flops go? A similar discrepancy
appears to be in the "real" system too.
Xilinx ISE Synthesis report except is pasted below, followed by the
myHDL code of the mock system.
By the way, I'm fairly new to working with python, myHDL, and the FPGA
design flow. So if I am doing something wrong, please let me know!
Hope this helps,
George
Release 7.1.04i - xst H.42
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <ram_inference_test_embedded>.
Related source file is "../../Synth_plus_UART_BUG.v".
WARNING:Xst:646 - Signal <_ADAP_0_buf_in1> is assigned but never used.
WARNING:Xst:646 - Signal <_ADAP_0_buf_in2> is assigned but never used.
WARNING:Xst:646 - Signal <_U_0_bufin> is assigned but never used.
WARNING:Xst:646 - Signal <_U_0_bufRxD> is assigned but never used.
Register <adapter_to_synth_data> equivalent to <addr> has been removed
Found 1-bit register for signal <audio_out>.
Found 1-bit register for signal <TxD>.
Found 8-bit adder for signal <$n0000> created at line 41.
Found 8-bit adder for signal <$n0001> created at line 46.
Found 8-bit adder for signal <$n0002> created at line 56.
Found 8-bit register for signal <_ADAP_0_c1>.
Found 8-bit register for signal <_SYNTH_0_c1>.
Found 2048-bit register for signal <_SYNTH_0_SYNTH_0_0_mem>.
Found 8-bit register for signal <_U_0_c1>.
Found 8-bit register for signal <addr>.
Found 1-bit register for signal <we>.
INFO:Xst:738 - HDL ADVISOR - 2048 flip-flops were inferred for signal
<_SYNTH_0_SYNTH_0_0_mem>. You may be trying to describe a RAM in a way
that is incompatible with block and distributed RAM resources available
on Xilinx devices, or with a specific template that is not supported.
Please review the Xilinx resources documentation and the XST user manual
for coding guidelines. Taking advantage of RAM resources will lead to
improved device usage and reduced synthesis time.
Summary:
inferred 2083 D-type flip-flop(s).
inferred 3 Adder/Subtractor(s).
Unit <ram_inference_test_embedded> synthesized.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : ram_inference_test_embedded.ngr
Top Level Output File Name : ram_inference_test_embedded
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 4
Macro Statistics :
# Registers : 4
# 1-bit register : 2
# 8-bit register : 2
# Adders/Subtractors : 2
# 8-bit adder : 2
Cell Usage :
# BELS : 1
# VCC : 1
# FlipFlops/Latches : 4
# FD : 2
# FDR : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 2
# OBUF : 2
=========================================================================
/// Begin code ////////////////////
# George Pantazopoulos
# ram_inference_test_embedded.py
from myhdl import *
# Dummy system set up to show that RAM inference does not occur under
# Xilinx ISE WebPACK 7.1.04i (Windows free version with
# XST as the synthesis tool)
# Tested with myHDL 0.5a1
# RAM construct copied verbatim from the example on the myHDL website.
# In a trivial (standalone) case, a RAM was inferred from this code
# using Xilinx XST but fails to do so when part of this system.
# Instead, it instantiates 2048 flip-flops and prints a warning to that
effect.
# ---------------------------
# Explanation of Mock system:
# ---------------------------
# PC serial port <-> UART <- bytestream -> Adapter <- SRAM-style ctrl ->
Synth
# A Uart turns a stream of bits into a stream of bytes.
# This byte stream is parsed by the Adapter into address, data, and control
# signals
# These control signals communicate with the Synth module and manipulate
# its internal RAM bank.
#
-----------------------------------------------------------------------------
# RAM construct copied verbatim from the example on the myHDL website.
def RAM(dout, din, addr, we, clk, depth=128):
""" Ram model """
mem = [Signal(intbv(0)[8:]) for i in range(depth)]
@always(clk.posedge)
def write():
if we:
mem[int(addr)].next = din
@always_comb
def read():
dout.next = mem[int(addr)]
return write, read
#
-----------------------------------------------------------------------------
def UART(clk, RxD, TxD, data_out, data_in):
c1 = Signal(intbv(0)[8:])
bufRxD = Signal(bool(0))
bufin = Signal(intbv(0)[8:])
@always(clk.posedge)
def UartProc():
c1.next = (c1 + 1) % 2**8
bufRxD.next = RxD
TxD.next = c1[0]
data_out.next = c1
bufin.next = data_in
return instances()
#
-----------------------------------------------------------------------------
# Mock-up bytestream to RAM protocol adapter
#
# Converts the stream of data bytes from the UART
# into a RAM write protocol.
def AdapterU2R(clk, uart_data_in, uart_data_out, ram_data_in,
ram_data_out, addr, we):
c1 = Signal(intbv(0)[8:])
buf_in1 = Signal(intbv(0)[8:])
buf_in2 = Signal(intbv(0)[8:])
@always(clk.posedge)
def dUtR():
c1.next = (c1 + 1) % 2**8
addr.next = c1
we.next = c1[0]
buf_in1.next = uart_data_in
uart_data_out.next = c1
buf_in2.next = ram_data_in
ram_data_out.next = c1
return instances()
#
-----------------------------------------------------------------------------
# Mock up audio synthesizer.
# Controlled by talking to its internal register bank as a RAM.
#
# Takes commands from a SRAM-like interface.
# data_in and data_out are for doing writes/reads to its
# internal register bank.
def Synth(clk, we, addr, data_in, data_out, audio_out):
c1 = Signal(intbv(0)[8:])
# The register bank
RAM_0 = RAM(dout=data_out,
din=data_in,
addr=addr,
we=we,
clk=clk,
depth=256)
@always(clk.posedge)
def SynthProcess():
c1.next = (c1 + 1) % 2**8
audio_out.next = c1[0]
return instances()
#
-----------------------------------------------------------------------------
clk = Signal(bool(0))
RxD = Signal(bool(0))
TxD = Signal(bool(0))
audio_out = Signal(bool(0))
def Top(clk, RxD, TxD, audio_out):
uart_to_adapter_data = Signal(intbv(0)[8:])
adapter_to_uart_data = Signal(intbv(0)[8:])
adapter_to_synth_data = Signal(intbv(0)[8:])
synth_to_adapter_data = Signal(intbv(0)[8:])
addr = Signal(intbv(0)[8:])
we = Signal(bool(0))
U_0 = UART(clk=clk,
RxD=RxD,
TxD=TxD,
data_out=uart_to_adapter_data,
data_in=adapter_to_uart_data)
ADAP_0 = AdapterU2R(clk=clk,
uart_data_in=uart_to_adapter_data,
uart_data_out=adapter_to_uart_data,
ram_data_in=synth_to_adapter_data,
ram_data_out=adapter_to_synth_data,
addr=addr,
we=we)
SYNTH_0 = Synth(clk=clk,
we=we,
addr=addr,
data_in=adapter_to_synth_data,
data_out=synth_to_adapter_data,
audio_out=audio_out)
return instances()
toVerilog.name = "ram_inference_test_embedded"
toVerilog(Top, clk, RxD, TxD, audio_out)
///// End code /////////
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