Re: [myhdl-list] Problems inferring RAM when it is buried in system

[Tom D. <td...@di...>]

George,

Could you include the MyHDL code for the example that doesn't work?

My experience with XST (ISE synthesis tool) is that it isn't very useful 
at this.

I will try it on Mentor Precision which is very good at inferring all 
the structures available in your target FPGA family.

You may need to use the new User Defined Verilog feature of MyHDL to 
include a hand coded Verilog module.

Tom




George Pantazopoulos wrote:

> Hi Jan,
>
>    Your trivial example of mapping a list of signals to a RAM memory 
> successfully infers a Distributed RAM under myHDL 0.5a1 and Xilinx ISE 
> 7.1.04i:
>
> def RAM(dout, din, addr, we, clk, depth=128):
>    """  Ram model """
>       mem = [Signal(intbv(0)[8:]) for i in range(depth)]
>
>    @always(clk.posedge)
>    def write():
>        if we:
>            mem[int(addr)].next = din
>                   @always_comb
>    def read():
>        dout.next = mem[int(addr)]
>           return write, read
>
>
> However, Xilinx ISE fails to infer a Distributed RAM if the ram logic 
> is buried in the system (input/output ports not exposed at top level).
>
> In my system, I have a UART (in myHDL) that feeds a RAM bank, such 
> that the RAM bank is not accessible directly from the outside world.
> I have boiled down the resulting Verilog code to just the code 
> necessary to show the problem.
>
> Xilinx ISE infers a Distributed RAM successfully from the Verilog code 
> I pasted below. However, merely commenting out the lines that bring 
> data_out to the top level causes ISE to fail to infer a Distributed 
> RAM. It wrongly creates 2048 flip-flops and prints a warning. Because 
> my RAM bank needs to be hidden within the system, I can not have 
> data_in or data_out listed as an input and output, respectively, at 
> the module level.
>
> Besides the possibility of a myHDL problem, am I going about things 
> wrong? All my work in myHDL so far has resulted in a single module( ); 
> section in the verilog code. Do I need to somehow make multiple modules?
>
> module Synth_plus_UART_BUG (
>    sysclk,
>    RxD,
>    TxD,
>    RxD_led,
>    audio_out,
>    debug_out,
>    data_in,
>    data_out,   // commenting this out causes RAM inference to fail
> );
>
> input sysclk;
> input RxD;
> output TxD;
> reg TxD;
> output RxD_led;
> reg RxD_led;
> output audio_out;
> reg audio_out;
> output [7:0] debug_out;
> reg [7:0] debug_out;
>
> input data_in;
> output data_out;   // commenting this out causes RAM inference to fail
>
> reg [7:0] addr;
>
>
> reg we;
>
> wire [7:0] data_out;
>
> reg [7:0] _S65X81_0_rbank [0:32-1];
> reg [7:0] _S65X81_0_S65X81_0_0_mem [0:256-1];
>
> always @(posedge sysclk) begin: _Synth_plus_UART_BUG_S65X81_0_RAM_0_write
>    if (we) begin
>        _S65X81_0_S65X81_0_0_mem[addr] <= data_in;
>    end
> end
>
>
> assign data_out = _S65X81_0_S65X81_0_0_mem[addr];
>
>
> endmodule
>
>
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