Re: [myhdl-list] Re: Problems inferring RAM when it is buried in system

[George P. <ge...@ga...>]

Hi Jan,

         I am using the free Xilinx ISE 
WebPACK(http://www.xilinx.com/ise/logic_design_prod/webpack.htm). The 
latest version is 7.1.04i (which is what I am using). I would recommend 
installing it, even if you don't use a Xilinx part at the moment. You 
can choose to only synthesize (right click the Synthesize-XST item in 
the list of processes and select Run) and see what is being inferred 
when you view the synthesis report in the Design Summary. You don't need 
to do any other steps of the FPGA implementation. You probably need my 
device stats. I am using the xc3s1000 device, speed grade -4, package 
type ft256. You can see the templates that ISE looks for when inferring 
components if you select the menu Edit->Language Templates.

And yes, I was having the same problem with the shift register you 
showed me in a previous email. It would infer on a standalone example, 
but not if it was buried inside my system.

The warning I get is:

 "INFO:Xst:738 - HDL ADVISOR - 2048 flip-flops were inferred for signal 
<_S65X81_0_S65X81_0_0_mem>. You may be trying to describe a RAM in a way 
that is incompatible with block and distributed RAM resources available 
on Xilinx devices, or with a specific template that is not supported. 
Please review the Xilinx resources documentation and the XST user manual 
for coding guidelines. Taking advantage of RAM resources will lead to 
improved device usage and reduced synthesis time."

Even though my small example doesn't necessarily prove my statement, I 
have been watching the Synthesis Report when I synthesize my entire 
system, and no Distributed RAMs or shift registers are inferred. But 
they are inferred when I try synthesizing trivial examples. I'd like to 
provide you with a more complete example. Is there something specific 
you'd like to see? This is a crucial feature and I've come so far with 
myHDL already, thanks to your good work. I'd like to help you get it 
working.

Thanks,
George

> George Pantazopoulos wrote:
>
>> However, Xilinx ISE fails to infer a Distributed RAM if the ram logic 
>> is buried in the system (input/output ports not exposed at top level).
>
>
> That's quite surprizing, because I don't see the technical
> reason behind it, and it would also severely restrict the usefulness
> of the RAM inference feature. I assume other kinds of embedded
> structures are inferred properly (counters, shift registers ...)
>
> Now, I don't have Xilinx installed so I can't experiment myself. BTW, is
> this something that I could check with the free version? In that
> case, I'll install it here.
>
> Can other Xilinx users confirm this, perhaps with other (more recent?)
> ise versions, before we start looking for workarounds?
>
> Note that the small example you give doesn't prove your statement
> above: it merely shows that RAM inference fails when the output
> port is not connected at all. (In fact, I would have expected
> that the synthesis tool removes all logic in that case.)
> But I assume that the RAM output is properly connected in the
> embedded case, because otherwize the Verilog convertor would
> have turned it into an output.
>
> Jan
>