[myhdl-list] Re: Problems inferring RAM when it is buried in system

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

> However, Xilinx ISE fails to infer a Distributed RAM if the ram logic is 
> buried in the system (input/output ports not exposed at top level).

That's quite surprizing, because I don't see the technical
reason behind it, and it would also severely restrict the usefulness
of the RAM inference feature. I assume other kinds of embedded
structures are inferred properly (counters, shift registers ...)

Now, I don't have Xilinx installed so I can't experiment myself. BTW, is
this something that I could check with the free version? In that
case, I'll install it here.

Can other Xilinx users confirm this, perhaps with other (more recent?)
ise versions, before we start looking for workarounds?

Note that the small example you give doesn't prove your statement
above: it merely shows that RAM inference fails when the output
port is not connected at all. (In fact, I would have expected
that the synthesis tool removes all logic in that case.)
But I assume that the RAM output is properly connected in the
embedded case, because otherwize the Verilog convertor would
have turned it into an output.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com