[myhdl-list] Re: Asynchronous receiver strange problem

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> Hi all,
> 
> I'm having a strange problem testing my UART in-silico. I don't believe it
> is related to my overall design or myHDL. I'm hoping maybe someone has
> come across this before.
> 

I suggest to seek help on comp.lang.fpga for issues such as this. It's
quite active and I think you have a good chance of getting help.

Of course, you'll have to illustrate the issue using the generated
Verilog, at least for the time being :-)

Jan

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