Re: [myhdl-list] Asynchronous receiver strange problem

[Haitao Z. <ha...@gm...>]

You didn't give much detail on what LEDs are lighting up and what are
not, but anyway this is not a list to debug designs. One thing you
want to consider is how fast you are clocking the shift registers.
Your eyes and the LEDs can't respond to the normal clock rate used in
the digital design. You can only see relatively static signals.

Haitao

On 11/23/05, George Pantazopoulos <ge...@ga...> wrote:
>
> Hi all,
>
> I'm having a strange problem testing my UART in-silico. I don't believe i=
t
> is related to my overall design or myHDL. I'm hoping maybe someone has
> come across this before.
>
> I have verified (in simulation, as well as in hardware using LEDs and my
> o-scope) that my Receiver goes through all the state transitions for an
> incoming serial stream. It even appears to be shifting the correct data
> into the Shift Register.
>
> My Asynchronous Receiver module has an 8-bit debug_out port that I connec=
t
> to 8 LED's on my Digilent Spartan3 FPGA dev board. A DebugProcess
> continually outputs any internal signals I choose to observe.
>
> When I try to display all eight bits of the shift register using the
> debug_out port, no LED's light up on my board. But if I display four of
> the Shift Register bits and four of the state bits, then the LED's light
> up just fine!
>
> In fact, I can even dislay seven of the eight bits correctly, as long as
> the other bit is displaying state (All LED's stay off if I make the
> remaining bit a constant 0). I can reliably reproduce this effect. What i=
n
> the world is going on here?
>
> I'm using the Digilent Spartan3 FPGA dev board, with Xilinx ISE 7.1i on
> Windows XP, with myHDL 0.5dev4.
>
> Changing the drive strength of the FPGA's LED output pins from 12ma to
> 24ma did not help.
>
> ----------------------------------------
> Excerpt from my Receiver design:
> (indentation is not necessarily correct)
> ----------------------------------------
>
> state =3D Signal(intbv(0)[4:])
> shift_reg =3D Signal(intbv(0)[8:])
>
> @always(clk.posedge)
> def DebugProcess():
>
> # This fails to light up any LED's on my dev board
> #    debug_out.next[0] =3D shift_reg[0]
> #    debug_out.next[1] =3D shift_reg[1]
> #    debug_out.next[2] =3D shift_reg[2]
> #    debug_out.next[3] =3D shift_reg[3]
>
> #    debug_out.next[4] =3D shift_reg[4]
> #    debug_out.next[5] =3D shift_reg[5]
> #    debug_out.next[6] =3D shift_reg[6]
> #    debug_out.next[7] =3D shift_reg[7]
>
> # This lights up the LED's ok!
> #    debug_out.next[0] =3D shift_reg[0]
> #    debug_out.next[1] =3D shift_reg[1]
> #    debug_out.next[2] =3D shift_reg[2]
> #    debug_out.next[3] =3D state[3] # NOTE: state here makes it work
>
> #    debug_out.next[4] =3D shift_reg[0]
> #    debug_out.next[5] =3D shift_reg[1]
> #    debug_out.next[6] =3D shift_reg[2]
> #    debug_out.next[7] =3D shift_reg[3]
>
>
> # This lights up the LED's ok also!
>     debug_out.next[0] =3D state[0]
>     debug_out.next[1] =3D state[1]
>     debug_out.next[2] =3D state[2]
>     debug_out.next[3] =3D state[3]
>
>     debug_out.next[4] =3D shift_reg[0]
>     debug_out.next[5] =3D shift_reg[1]
>     debug_out.next[6] =3D shift_reg[2]
>     debug_out.next[7] =3D shift_reg[3]
>
>
> --------------------------------------------
>
> Thanks,
>
> --
> George Pantazopoulos
> http://www.gammaburst.net
>
>
>
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