[myhdl-list] Feedback on clk.posedge style issue

[Jan D. <ja...@ja...>]

Hi all:

For the 0.5 release, I'm thinking to make a few style changes.

One change involves edge specifiers. In particular, I would like
to suggest the following usage (with 'clk' any kind of signal):

    clk.posedge (instead of posedge(clk))
    clk.negedge (instead of negedge(clk))

No code changes are required: these attributes always existed
and the functions were wrappers around them. Probably I was
thinking to use the functions to make it look more like Verilog,
but now I consider this to be a very weak argument.

The arguments for this style change are, in order of increasing
significance:

- one character less to type
- more object-oriented style
- no brackets, which is better for clarity
- no function call overhead (Function calls are expensive. Note
that these functions may be called over and over again during
simulation.)

To introduce this, I would not touch any MyHDL code in 0.5,
so the functions would remain available. However, they would
be removed from the documentation, and all examples would
be updated to the new style. The functions will be deprecated
and removed in later releases.

If you *disagree*, please respond quickly.

Regards,

Jan

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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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