[myhdl-list] Re: signed arithmetic

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Hi all:
> 
> I have added support for Verilog conversion of signed arithmetic to the
> development version.

The original approach has been discarded. The new approach is described
here:

 
http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_arithmetic

It is available for testing in 0.5dev5.

The test suite contains more tests, and more cases are covered. Also,
I think the implementation has everything in place to make it a
robust solution. However,  this is tricky stuff and there may still be
cases that fail. You are welcome to try to make it fail!

On the other hand, when this becomes robust, I believe we have
created significant added value for the poor Verilog designer
that tries to get his negative numbers right.

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     From Python to silicon:
     http://myhdl.jandecaluwe.com