[myhdl-list] Re: Feedback request: User-defined Verilog code

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Tom Dillon wrote:
> 
>> Jan Decaluwe wrote:
>>
>>>
>>> Think about it this way: after the user-defined code is inserted, how
>>> should the (driven) signal be declared in Verilog? If it's driven by
>>> an assign or if it's connected to an output port of an instantiated
>>> module, it should be a wire. But if it's driven from an always block,

I have added more info on this to the MEP page.

I have also released snapshot 0.5dev4 with this feature.

Jan

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