[myhdl-list] Re: 0.5dev3 testing

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> 
> 
> Jan Decaluwe wrote:
> 
>> Tom Dillon wrote:
>>
>>> I had been using the following:
>>>
>>> Signal(intbv(0,min=0,max=2))
>>>
>>> to get a 1 bit register or wire.
>>>
>>> With the development version I get a 2 bit signal. Is that intentional?
>>>
>>> I thought the range should be min <= Num < max.
>>
>>
>>
>> Tom:
>>
>> To understand whether this is expected or not, can you please tell
>> me if you have *somewhere* in your MyHDL code, an intbv that can
>> have negative values?
>>
> Yes.

Tom:

In that case, it was not possible to convert with 0.4, so you already
gain :-)

What I expect is that you don't just get a 2 bit signal, but a *signed*
2 bit signal. For a signed representation of just 0 and 1, you do need
an additional sign bit (which will be zero).

Of course the question is - why a signed representation for a positive
intbv? I have tried to answer that here:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5#support_for_signed_arithmetic

Please review this. The point is that it's tricky to get signed right
in Verilog - using signed as a "default" for intbv representation
helps in getting it right.

Note that there are special cases, such as slicing, indexing and also
single bit signals. The latter is relevant to you. As a matter of style,
I suggest to use Signal(bool()) to represent single bit signals. It's
more efficient, less typing, and it is clearer. You dont' lose anything
in terms of operations because bool is a subtype of int in Python.

Moreover, bool() is treated specially by the convertor - the reasoning
is that signed/unsigned clearly doesn't make a lot of sense in this
case. Moreover, you want signals like clocks and resets to be single
bit (unsigned) regs in Verilog. So if you use bool(), you will still
get a single bit unsigned reg/wire in Verilog.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
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