[myhdl-list] one more for 0.5dev3

[Tom D. <td...@di...>]

I found one more hierarchical related problem in 0.5dev3, this one I 
think is new to the development version.

The following code:

def add(x,a,b) :
  def logic() :
    x.next = a + b
  L0 = always_comb(logic)
  return L0

def add4(x,a,b,c,d) :
  xL = [Signal(intbv(0,min=-2**(width+2),max=2**(width+2))) for i in 
range(2)]

  A0 = add(xL[0],a,b)
  A1 = add(xL[1],xL[0],c)
  A2 = add(x, xL[1],d)

  return instances()

def TestModule(x,a,b,c,d,e) :
  x0 = Signal(intbv(0,min=-2**(width+2),max=2**(width+2)))

  A0 = add4(x0,a,b,c,d)
  A1 = add4(x,x0,e,a,b)

  return instances()



The Verilog generated by toVerilog has reg name conflicts on the xL list 
of signals in add4().

I don't have a fix for this one, but it looks like it uses the wrong 
hierarchy in the signal name, the same one for each occurrence of it.

Let me know if you need more information.

Tom