[myhdl-list] 0.5dev3 Verilog signal name conflict

[Tom D. <td...@di...>]

This isn't new to the development version, but I just ran into it again 
while testing 0.5dev3.

The following code produces a wire name conflict in the toVerilog 
generated Verilog code.

width = 8

def add(x,a,b) :
  def logic() :
    x.next = a + b
  L0 = always_comb(logic)
  return L0

def add3(x,a,b,c) :
  x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))
  A0 = add(x0,a,b)
  A1 = add(x,x0,c)

  return instances()

def TestModule(x,a,b,c,d,e) :
  x0 = Signal(intbv(0,min=-2**(width-1),max=2**(width-1)))

  A0 = add3(x0,a,b,c)
  A1 = add3(x,x0,d,e)

  return instances()


The following changes in _toVerilog/_analyze.py fix the problem. This is 
from line 83.

# TPD fix to problem caused by not popping high enough in the hierarchy.
prefixes = prefixes[:curlevel-1]
prefixes.append(name)
# old way
# prefixes = prefixes[:curlevel]


Let me know if you need any more information.

Tom