[myhdl-list] Re: Feedback request: User-defined Verilog code

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan Decaluwe wrote:
> 
>>
>> Think about it this way: after the user-defined code is inserted, how
>> should the (driven) signal be declared in Verilog? If it's driven by
>> an assign or if it's connected to an output port of an instantiated
>> module, it should be a wire. But if it's driven from an always block,
> 
> 
> Yes, I see that now.  Would it make sense to default it to "wire"? I 
> think that would be the most common type, at least from my perspective.

In the MyHDL conversion logic, there is a different default already:
namely that a signal is not driven at all. In that case, it will be
either a top-level input, or an undriven wire. In the latter case, a
warning is issued, and an assignment keeps the wire to a constant value. 
I think it is clear why this default makes sense: the convertor can
normally detect whether a signal is driven, and otherwise, the default
is correct - except in the special case of user-defined code.

I'm hoping to be able to keep the default as it is, and ask more help
from the user for the special case. I've not yet found a better
solution.

The "driven" attribute was already used internally for inference of
input, outputs, wire, regs. What I did now is simply make it a public
attribute that can be manipulated by the user, to resolve issues with
user-defined code.

Jan

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