Re: [myhdl-list] Re: Feedback request: User-defined Verilog code

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> Think about it this way: after the user-defined code is inserted, how
> should the (driven) signal be declared in Verilog? If it's driven by
> an assign or if it's connected to an output port of an instantiated
> module, it should be a wire. But if it's driven from an always block,

Yes, I see that now.  Would it make sense to default it to "wire"? I 
think that would be the most common type, at least from my perspective.

Tom