[myhdl-list] Re: Feedback request: User-defined Verilog code

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> Funny I was reading that late last night and it was half complete, you 
> must have been working on it.

Yes, with a wiki it all happens in real time!

> That looks good to me, and more general (better) than what I was thinking.
> 
> In your example, I am assuming that instead of the assign you could have 
> any Verilog statements. Such as a module instantiation using MyHDL 
> signals as connections?

Yes. You can do instantiations, but also anything that can occur where
instantiations can occur. (I don't know whether this formulation
is clear). I'm not sure whether that is equivalent to "any verilog
statement" though.

> One question, what is the difference between the wire and reg for 
> .driven? I'm not used to worrying about that when connecting Verilog 
> modules together.

Think about it this way: after the user-defined code is inserted, how
should the (driven) signal be declared in Verilog? If it's driven by
an assign or if it's connected to an output port of an instantiated
module, it should be a wire. But if it's driven from an always block,
it should be a reg.

Perhaps one could think that this could be simplified by only allowing
instantiations, which only require wires. But that doesn't solve the
issue: you still need to tell the convertor which signals are supposed
to be driven by the block. (You would have to say "sig.driven = True"
or something). Otherwise, the convertor will infer an undriven
wire and issue a warning.

Note that normally in MyHDL, you don't have to specify what "inputs"
and "outputs" are - it's all inferred from usage. So this is an
exception.

Note also that a similar issue doesn't exist with signals that are
merely used by the block: everything can be inferred
from the context.

Finally, note that if you forget to set the attribute, or if you
set it to an incorrect value, you will always find out: the convertor
will issue warnings, and/or the Verilog code will not compile. So
I guess this is acceptable.

Let me know if this is acceptable, whether it's clear, and otherwise,
how to explain it better.

Regards,

Jan

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