Re: [myhdl-list] Feedback request: User-defined Verilog code

[Tom D. <td...@di...>]

Jan,

Funny I was reading that late last night and it was half complete, you 
must have been working on it.

That looks good to me, and more general (better) than what I was thinking.

In your example, I am assuming that instead of the assign you could have 
any Verilog statements. Such as a module instantiation using MyHDL 
signals as connections?

One question, what is the difference between the wire and reg for 
.driven? I'm not used to worrying about that when connecting Verilog 
modules together.

Tom



Jan Decaluwe wrote:

> Hi:
>
> I have made (and implemented) a proposal for including user-defined
> Verilog code during the conversion.
>
> I have not yet made a snapshot, because I would like to have feedback
> first. Please read:
>
>    http://myhdl.jandecaluwe.com/doku.php/meps:mep-101
>
> and provide feedback.
>
> Regards,
>
> Jan
>