[myhdl-list] Feedback request: User-defined Verilog code

[Jan D. <ja...@ja...>]

Hi:

I have made (and implemented) a proposal for including user-defined
Verilog code during the conversion.

I have not yet made a snapshot, because I would like to have feedback
first. Please read:

    http://myhdl.jandecaluwe.com/doku.php/meps:mep-101

and provide feedback.

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com