[myhdl-list] Re: myHDL success: synthesized a UAR(T)

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:

>      I used the Verilog UART design on fpga4fun.com as a reference, and 
> some posts from comp.arch.fpga, and sci.electronics.design for further 
> guidance. With this knowledge, I recreated the asynchronous receiver in 
> myHDL. It took some time and effort, because I wanted to do things right 
> and understand the concepts involved, not just blindly port code. A 
> significant thing that ate up time was the almost impossible to 
> understand error messages when something was wrong in the code. Is that 
> something you could improve?

Probably, but only if you let me know the full details. The goal is that
the error messages should be crystal-clear, and currently I think
they are :-)

Jan

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