[myhdl-list] myHDL success: synthesized a UAR(T)

[George P. <ge...@ga...>]

Jan,

     The combination of python, myHDL, and GTKWave is powerful. With 
these tools, I succeeded in synthesizing a UART, and late last night I 
watched with joy as the LED's on my FPGA board lit up to represent the 
value of the bytes sent (at 57600 baud) from my PC!

      I used the Verilog UART design on fpga4fun.com as a reference, and 
some posts from comp.arch.fpga, and sci.electronics.design for further 
guidance. With this knowledge, I recreated the asynchronous receiver in 
myHDL. It took some time and effort, because I wanted to do things right 
and understand the concepts involved, not just blindly port code. A 
significant thing that ate up time was the almost impossible to 
understand error messages when something was wrong in the code. Is that 
something you could improve?

I learned a great deal, and am more comfortable with myHDL and hardware 
design than ever now. Now to tackle the transmit side of the UART! Keep 
up the great work on myHDL. It is clearly a success.

George