Re: [myhdl-list] Interfacing to existing Verilog/VHDL

[Tom D. <td...@di...>]

George,

I think what you are looking for is support for user defined Verilog 
code, slated for next release.

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

Tom


George Pantazopoulos wrote:

> Hi all,
>     Is it possible for me to connect (at the python level) my 
> myHDL-generated Verilog with some pre-existing Verilog/VHDL code (eg. 
> from OpenCores)?
>
> Thanks,
> George
>
>
>
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