[myhdl-list] Re: signed bit vectors

[Jan D. <ja...@ja...>]

Matt Ettus wrote:
> Tom Dillon wrote:
> 
>>Matt,
>>
>>The current version of toVerilog does not support signed numbers.
>>
>>It is in the works for the next release. Check out the new features:
>>
>>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
> 
> 
> 
> I'm not using toVerilog.  I am doing cosimulation with icarus, and
> negative numbers I send into the verilog side have x's in them (but not
> all the bits, just the upper ones).

As it happens, I am working on signed support for Verilog currently. It
was not yet supported for Verilog conversion (documented) and for
co-simulation (undocumented - don't know why). I deferred this because I 
thought it would be tricky. It is! (at the Verilog side).

I have found that Icarus is buggy with respect to signed support. See:

    http://groups.google.be/groups?q=Verilog+signed+arithmetic+Decaluwe

"Buggy" simply means that it doesn't what other Verilog simulators,
including the big ones, do. I am relying on Cver for this now.

Development version 0.5dev2 has Verilog co-simulation support for
negative intbv's (I need this to verify the Verilog conversion work).

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
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