[myhdl-list] Re: signed bit vectors
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From: Jan D. <ja...@ja...> - 2005-10-26 20:30:25
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David Brochart wrote:
> Yes, but you can also specify the range explicitly:
>
> s = Signal(intbv(0)[m : n])
>
> s would be a std_logic_vector(m - 1 downto n) in VHDL.
Actually, it's more like std_logic_vector(m-n-1 downto 0). However, the
typical usage pattern in this case would be with n=0.
I thought it was useful to add a FAQ entry for the original question:
http://myhdl.jandecaluwe.com/doku.php/faq
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Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
Electronic design with Python:
http://myhdl.jandecaluwe.com
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