Re: [myhdl-list] signed bit vectors

[Tom D. <td...@di...>]

Matt,

There are also a couple of changes required to _Cosimulation.py to pass 
the numbers properly.

I can send you my hacked version if you like.

Tom


Matt Ettus wrote:

>Tom Dillon wrote:
>  
>
>>Matt,
>>
>>The current version of toVerilog does not support signed numbers.
>>
>>It is in the works for the next release. Check out the new features:
>>
>>http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5
>>    
>>
>
>
>I'm not using toVerilog.  I am doing cosimulation with icarus, and
>negative numbers I send into the verilog side have x's in them (but not
>all the bits, just the upper ones).
>
>Matt
>
>
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