Re: [myhdl-list] signed bit vectors

[Tom D. <td...@di...>]

Matt,

The current version of toVerilog does not support signed numbers.

It is in the works for the next release. Check out the new features:

http://myhdl.jandecaluwe.com/doku.php/whatsnew:0.5

Tom



Matt Ettus wrote:

>nicran wrote:
>  
>
>>As I know, there is no way to specify the bitwidth, you can only
>>specify the default value of a bitvector.
>>
>>
>>2005/10/25, Matt Ettus <ma...@et...>:
>>
>>    
>>
>>>I just discovered MyHDL today, and it appears to be just what I've been
>>>looking for!  Thanks for making it and for documenting it so well!  I
>>>was able to get up and running with complex simulations in less than
>>>half a day.
>>>
>>>I just have a couple of questions -- Is there any way to make intbv's
>>>signed?  Also, how do I specify the bitwidth?
>>>      
>>>
>
>I just found how to set ranges, which is I guess the substitute for
>setting bitwidths.  However, when I set an intbv signal to a negative
>value, it is giving me X's in my verilog simulation.
>
>Any ideas?
>
>Thanks,
>Matt
>
>
>-------------------------------------------------------
>This SF.Net email is sponsored by the JBoss Inc.
>Get Certified Today * Register for a JBoss Training Course
>Free Certification Exam for All Training Attendees Through End of 2005
>Visit http://www.jboss.com/services/certification for more information
>_______________________________________________
>myhdl-list mailing list
>myh...@li...
>https://lists.sourceforge.net/lists/listinfo/myhdl-list
>
>  
>