Re: [myhdl-list] signed bit vectors

[David B. <dav...@fr...>]

Yes, but you can also specify the range explicitly:

s =3D Signal(intbv(0)[m : n])

s would be a std_logic_vector(m - 1 downto n) in VHDL.

David.



Selon Matt Ettus <ma...@et...>:

> David Brochart wrote:
> > Yes you can:
> >
> > http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-intbv.html
> >
>
> Do you mean that the bitwidth is specified implicitly through the min
> and max?
>
> Matt
>
>
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