[myhdl-list] Re: Xilinx ISE error: unexpected token: '='

[George P. <ge...@ga...>]

> 
> It's a mismatch between MyHDL and the point where I hoped that
> mainstream Verilog tools would be by now :-) Initial value assignments
> were introduced in Verilog 2001 but several tools don't seem to support
> them. I included them to try to avoid simulation mismatches at
> startup time with the MyHDL model.
> 
> However, it seems clear that I will have to take them out. It's probably
> not such a big deal provided initialiation is done properly by other
> means. I have done so in my current development toward 0.5.
> 
> You have 2 options: the first is to just go into the code (I assume
> you use 0.4.1) of toVerilog/_convert.py, and take out the initial value 
> assignments in function _writeSigDecls and method writeDeclaration.
> 
> Or, you can use the 0.5 development snapshot from
> 
>    http://myhdl.jandecaluwe.com/doku.php/snapshots
>

> The advantage here is that there are some new features that may
> especially be interesting for people doing FPGAs, such as support for
> RAM and ROM inferencing.

Thanks for the tip, and this RAM and ROM inferencing looks like it will 
be very handy! I will be checking out 0.5dev1 shortly.

>> FWIW, I'm a newbie both to python and myHDL, but with myHDL I have 
>> been able to get further in my project than I dreamed possible (I'm 
>> making a digital music synthesizer, and within two days I was up and 
>> running and playing with sounds coming out of my FPGA board!) I tired 
>> verilog, vhdl, and even confluence,  but myHDL is, for me, by far the 
>> best way to go!
> 
> 
> Good to hear! At some point, please consider adding some info about
> your project at the MyHDL web site (or ask me to do it.)

Will do, as soon as it takes a little more form :) You've done a great 
thing by developing myHDL. Do you have any help with it?

George