[myhdl-list] Re: Xilinx ISE error: unexpected token: '='

[Jan D. <ja...@ja...>]

George Pantazopoulos wrote:
> 
> 
> Hi all,
>    When I use a 'for' loop in one of my components, it produces verilog 
> code that doesn't compile as-is.
> Specifically, it produces in verilog "integer i = 0;", which causes an 
> error in Xilinx ISE (7.1.04i):
> 
> Xilinx ISE error
> -----------------
> Compiling verilog file "../../SYNTH_0.v"
> ERROR:HDLCompilers:26 - "../../SYNTH_0.v" line 41 unexpected token: '='
> 
> I can get it to compile and the circuit works fine if I manually edit 
> "integer i = 0;" to "integer i;". However, this is quite inconvenient. 
> Is the problem something I am doing? In myHDL? In Xilinx ISE? See below 
> for my myHDL code and the corresponding verilog output.

It's a mismatch between MyHDL and the point where I hoped that
mainstream Verilog tools would be by now :-) Initial value assignments
were introduced in Verilog 2001 but several tools don't seem to support
them. I included them to try to avoid simulation mismatches at
startup time with the MyHDL model.

However, it seems clear that I will have to take them out. It's probably
not such a big deal provided initialiation is done properly by other
means. I have done so in my current development toward 0.5.

You have 2 options: the first is to just go into the code (I assume
you use 0.4.1) of toVerilog/_convert.py, and take out the initial value 
assignments in function _writeSigDecls and method writeDeclaration.

Or, you can use the 0.5 development snapshot from

    http://myhdl.jandecaluwe.com/doku.php/snapshots

The advantage here is that there are some new features that may
especially be interesting for people doing FPGAs, such as support for
RAM and ROM inferencing.

> FWIW, I'm a newbie both to python and myHDL, but with myHDL I have been 
> able to get further in my project than I dreamed possible (I'm making a 
> digital music synthesizer, and within two days I was up and running and 
> playing with sounds coming out of my FPGA board!) I tired verilog, vhdl, 
> and even confluence,  but myHDL is, for me, by far the best way to go!

Good to hear! At some point, please consider adding some info about
your project at the MyHDL web site (or ask me to do it.)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Electronic design with Python:
     http://myhdl.jandecaluwe.com