[myhdl-list] Xilinx ISE error: unexpected token: '='

[George P. <ge...@ga...>]

Hi all,
    When I use a 'for' loop in one of my components, it produces verilog 
code that doesn't compile as-is.
Specifically, it produces in verilog "integer i = 0;", which causes an 
error in Xilinx ISE (7.1.04i):

Xilinx ISE error
-----------------
Compiling verilog file "../../SYNTH_0.v"
ERROR:HDLCompilers:26 - "../../SYNTH_0.v" line 41 unexpected token: '='

I can get it to compile and the circuit works fine if I manually edit 
"integer i = 0;" to "integer i;". However, this is quite inconvenient. 
Is the problem something I am doing? In myHDL? In Xilinx ISE? See below 
for my myHDL code and the corresponding verilog output.

FWIW, I'm a newbie both to python and myHDL, but with myHDL I have been 
able to get further in my project than I dreamed possible (I'm making a 
digital music synthesizer, and within two days I was up and running and 
playing with sounds coming out of my FPGA board!) I tired verilog, vhdl, 
and even confluence,  but myHDL is, for me, by far the best way to go!

Thanks!
George
http://www.gammaburst.net

offending myHDL input
------------------------

# Alternately makes all bits in wave_out 0, then 1
def Pulser(clock, reset, enable, count_in, duty_cycle, wave_out):

    OUTPUT_BITS = len(wave_out)
   
    def PulserProcess():
        while 1:
            yield posedge(clock)

            for i in range(OUTPUT_BITS):

                if count_in == 0:
                    wave_out.next[i] = 1
                elif count_in == duty_cycle:
                    wave_out.next[i] = 0
       
    return PulserProcess()


Xilinx ISE output
-----------------

always @(posedge clock) begin: _MYHDL4_BLOCK
    integer i = 0;
    for (i=0; i<12; i=i+1) begin
        if ((_WAVE_0_accum_out == 0)) begin
            wave0_out[i] <= 1;
        end
        else if ((_WAVE_0_accum_out == sweep0_out)) begin
            wave0_out[i] <= 0;
        end
    end
end