[myhdl-list] Some thoughts on toVerilog, toVHDL, etc.

[<dan...@we...>]

Hi,

When browsing for netlists I ran across this page about a free netlist 
format:

	http://www.confluent.org/wiki/doku.php?id=fnf:index

This gave me an idea and I was wondering how feasible this really is? 
How difficult would it be in MyHDL instead of creating individual 
toVerilog, toVHDL, etc. modules, to go through a neutral netlist and 
from there create HDL code?

I think this netlist format steamed from the confluence language, which 
I am not really familiar with. However, I read that it is possible to 
convert confluence in all types of other languages, like Verilog, VHDL, 
but also programming language like C. This is also pictured in the web 
link I gave above. Now I was wondering when the netlist format is the 
key to that flexibility, whether MyHDL could take favor of developments 
already done in that area?


Cheers,

Guenter