[myhdl-list] Re: toVerilog dynamic top level name
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From: Jan D. <ja...@ja...> - 2005-09-05 09:35:18
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Tom Dillon wrote:
> Jan Decaluwe wrote:
>>
>> Back to our original issue: if as user wants set
>> the instance name to another value than the default,
>> the usage model would be:
>>
>> toVerilog.name = "myInstanceName"
>> inst = toVerilog(func, *args, **kwargs)
>>
>> I'm inclined to implement it like that - so hurry
>> with feedback if you want to stop me :-)
> This would work, although it seems like logically a class is better for
> that. I wouldn't think to set an attribute to a function, even though
> python supports it. I am OK with it though, would get used to it, and
> probably learn and use that feature of python in other circumstances.
Perhaps we have a misunderstanding?
In the code above, toVerilog actually is an instance of a
ToVerilogConvertor class. So you do get all the goodies
of classes, instances, and attributes. However, the class
would support the special __call__ attribute, which
means you can call toVerilog as if it were a function.
When I think of it further, I think this way to do it
provides the right balance between backward compatibility
and additional power required to customize toVerilog's
behavior.
> Let me throw in a couple more ideas:
>
> a 2nd function,
>
> inst = toVerilogNamed(func,name,*args,**kwargs)
>
> or just changing toVerilog to that format, throwing backward
> compatibility to the wind. You could allow "" or None to use the default
> as it is now.
If find neither proposal attractive. It is very well possible
that we will want to support additonal options than "name"
in the future. The proposals above don't address that.
Moreover, I believe that default usage should really be
as simple as going from:
inst = func(*args, **kwargs)
to:
inst = toVerilog(func, *args, **kwargs)
without having to explain about additional capabilities. For
many users and in many cases, this usage will be enough.
It is appropriate that the more sophisticated user needs
to learn a little more (e.g. that toVerilog is actually
in instance).
Jan
--
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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Using Python as a hardware description language:
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