Re: [myhdl-list] Re: toVerilog dynamic top level name

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> I propose to drop the current instance name inference mechanism.
> Instead, I would use func.func_name as the default name.
> (This is the name that appears in the def statement).
> Technically, this is more correct, as the Verilog file
> doesn't contain an instance, but a module.
>
> Additionally, a named parameter "name" would be introduced
> in toVerilog, that can be used to override the default name
> in any desired way.

That would work great, if you don't like the default name you can 
substitute in what you want.

Can you do this in python? 

def toVerilog(func,name=None, *args,**kwargs)

It seems like

toVerilog(add,"addTopName",x,a,b,clk)

Could get name and *args confused? Maybe I'm confused...

>
> [For completeness: the current implementation also infers
> the name if it is subscripted, e.g. inst[0]. But this
> is probably an exotic feature that nobody uses and
> therefore would not be missed.]

You could still use name="inst[%s]"%i or something like that to take 
care of that.

BTW, I never did figure out in Python how to make a dynamic variable 
name. I gave up and hacked my local copy of MyHDL to pass a sting to 
toVerilog with the name.

Tom