[myhdl-list] Re: Tristate logic (newbie question)

[Jan D. <ja...@ja...>]

José Pedro Matos wrote:
> hello to all.
> 
> Is any solution for the tristate question been resolved?

Bom dia, tudo bem? :-)

Not much has been done - I still hate tristates as much as then :-)
However, in the development version, I have started to support None as
as a value for an intbv slice, by removing the bound checks if
the value is None. This was done to support things like:

    intbv()[8:]

in list of signal definitions (for memory inference in toVerilog).

> 
> The first example that i make in verilog and in vhdl is to put a value
> in the data bus when READ_Z and ChipSelect_Z go down and then put the
> bus in high impedance when the chip is not selected. I see it work fine.
> I'm happy.
> 
> I tried to generate the same hdl in myhdl. Not happy.
> 
> I would like to use myhdl, because python is on my self-learning path,
> because for what i've read i believe in xp programming and i see lot of
> good things comming from python people.
> 
> Can someone help me?
> I could try hack the code. Has someone done that?

Hacking the code is fine, a discussion on how things should work,
in full detail, even better :-)

> Why there is no CVS for this project?

(Note: I do use CVS locally to manage the source code.)

To main reasons why there is not yet a public CVS repository:

1. In my judgement, it was not the most urgent functionality
for the project, considering the stage it is in.
2. I hoped that by the time a public repo would be useful, there
would be a better alternative to CVS available, perhaps a
distributed version control system.

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html