[myhdl-list] Re: toVerilog dynamic top level name

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> I was trying to develop a class to handle the details of synthesizing a 
> MyHDL function. This was all fine except for one thing that I am stuck on.
> 
> To use toVerilog, you do:
> 
> topName = toVerilog(func,*args,**kwargs)
> 
> I could not get this to work with a dynamic topName. I tried the 
> following and some other attempts as well.
> 
> exec('%s = toVerilog(func,*args,**kwargs)'%(name)
> 
> func, is the name of the MyHDL function to use, *args, **kwargs are the 
> signal and parameter connections  to that function. name is a string 
> representation of what the top level name should be.
> 
> I don't think this is a python limitation, either my error or  because 
> of how toVerilog figures out the top level name.
> 
> Any ideas?

Yes - it's ugly and it is caused by my exagerated attempts
to make things "easier" for a user :-)

My goal was to encourage the user to simulate the converted
design (because good simulation catches more errors
than the convertor does.) That's why toVerilog returns
an instance, and why I wanted to use the instance name
when naming the converted Verilog files.

So, in:

    topName = toVerilog(func,*args,**kwargs)

I need to find the string "topName". If you think about
it, you'll understand why this gets ugly. toVerilog
does crazy things: it gets its own frame info, finds
the source file, gets to the line of its own call,
and parses that to get the instance name ...
And of course, this all fails when the scheme above is not
followed (e.g. when not using the returned instance value,
or with dynamic naming).

So I apologize :-) and propose to change this to something
less "clever". Now, an issue to consider is that this would
introduce some backward incompability. So, to all those
interested: please review the following proposal carefully and
provide feedback.

I propose to drop the current instance name inference mechanism.
Instead, I would use func.func_name as the default name.
(This is the name that appears in the def statement).
Technically, this is more correct, as the Verilog file
doesn't contain an instance, but a module.

Additionally, a named parameter "name" would be introduced
in toVerilog, that can be used to override the default name
in any desired way.

For consistency, a similar thing should be done with
traceSignals.

This solution would be more general with much simpler
code. However, as I said, existing code would need to
be modified as the Verilog files will have different
names than before (by default).

[For completeness: the current implementation also infers
the name if it is subscripted, e.g. inst[0]. But this
is probably an exotic feature that nobody uses and
therefore would not be missed.]

Feedback welcome.

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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