[myhdl-list] Re: Tristate logic (newbie question)

[P. M. <jos...@pt...>]

#################################################################
# brouter.py EXAMPLE code
#################################################################
from __future__ import generators
from myhdl import Signal, Simulation, delay, traceSignals, intbv,
toVerilog


def brouter( clk, clk2m, mclk, cs_z, liu_thz, rd_z, dados, teste,
rs232_tx, rs232_rx, addr):
        """ brouter
            um exemplo simples em myhdl

            input clk; CLK_CPU
            input clk2m; CLK_2048MHz
            output mclk; CLK_LIU_MCLK
            input cs_z; CS_FPGA_Z
            output liu_thz; LIU_TH_Z
            input rd_z; RD_Z
            inout [7:0] dados; DADOS
            output teste; pino de test
            output rs232_rx; RX uC porta serie 2
            input rs232_tx; TX uC porta serie 2
            input [19:0] addr; ADDR
            
        """
#       teste.next = clk.val
#       mclk.next = clk2m.val
#       liu_thz.next = intbv(0)[1:]
#       rs232_rx.next = rs232_tx.val

        def brouterProcess():
                while 1:
                        yield cs_z, rd_z
                        if (cs_z == 0) and (rd_z == 0):
                                dados.next = intbv(0xA5)[8:]
                        else:
                                dados.next = intbv(None)[8:] #high
impedance assign

        return brouterProcess()


clk= Signal(bool(0))
clk2m= Signal(bool(1))
mclk = Signal(bool(0))
cs_z = Signal(bool(1))
liu_thz = Signal(bool(1))
rd_z = Signal(bool(1))
dados = Signal(intbv(0)[8:])
teste = Signal(bool(0))
rs232_tx = Signal(bool(1))
rs232_rx = Signal(bool(0))
addr = Signal(intbv(0)[20:])

dados.next = intbv(val=None,_nrbits=8)
dados.next = intbv(None)[8:]

if dados.val._nrbits == 0:
        print "len: 0\n"
else:   
        print "len: %d \n" % (dados.val._nrbits)

br_inst= toVerilog(brouter, clk, clk2m, mclk, cs_z, liu_thz, rd_z,
dados, teste, rs232_tx, rs232_rx, addr)

#################################################################
# GENERATED CODE
#################################################################

module br_inst (
    clk,
    clk2m,
    mclk,
    cs_z,
    liu_thz,
    rd_z,
    dados,
    teste,
    rs232_tx,
    rs232_rx,
    addr
);

input clk;
input clk2m;
input mclk;
input cs_z;
input liu_thz;
input rd_z;
output [7:0] dados;
reg [7:0] dados;
input teste;
input rs232_tx;
input rs232_rx;
input [19:0] addr;



always @(cs_z or rd_z) begin: _MYHDL1_BLOCK
    if (((cs_z == 0) && (rd_z == 0))) begin
        dados <= 8'ha5;
    end
    else begin
        dados <= 8'hZ;
    end
end

endmodule


############################ CUT ME #############################
# _intbv.py.patch
############################ CUT ME #############################
jmatos - ~/work/hdl/myhdl-0.4.1/myhdl $ diff -u --new-file
_intbv.py /usr/lib/python2.3/site-packages/myhdl/_intbv.py
--- _intbv.py   2004-12-29 13:37:59.000000000 +0000
+++ /usr/lib/python2.3/site-packages/myhdl/_intbv.py    2005-08-31
13:54:36.000000000 +0000
@@ -71,14 +71,13 @@
     min = property(_get_min, None)
 
     def _checkBounds(self):
-        if self._max is not None:
-            if self._val >= self._max:
-                raise ValueError("intbv value %s >= maximum %s" %
-                                 (self._val, self._max))
-        if self._min is not None:
-            if self._val < self._min:
-                raise ValueError("intbv value %s < minimum %s" %
-                                 (self._val, self._min))
+       if self._val is not None:
+               if self._max is not None:
+                       if self._val >= self._max:
+                               raise ValueError("intbv value %s >=
maximum %s" % (self._val, self._max))
+                       if self._min is not None:
+                       if self._val < self._min:
+                               raise ValueError("intbv value %s <
minimum %s" % (self._val, self._min))
 
 
     # hash
@@ -113,7 +112,10 @@
     def __getitem__(self, key):
         if isinstance(key, int):
             i = key
-            res = intbv((self._val >> i) & 0x1, _nrbits=1)
+           if self._val is None:
+               res= intbv(None,_nrbits=1)
+           else:
+               res = intbv((self._val >> i) & 0x1, _nrbits=1)
             return res
         elif isinstance(key, slice):
             i, j = key.start, key.stop
@@ -127,7 +129,10 @@
             if i <= j:
                 raise ValueError, "intbv[i:j] requires i > j\n" \
                       "            i, j == %s, %s" % (i, j)
-            res = intbv((self._val & (1L << i)-1) >> j, _nrbits=i-j)
+           if self._val is None:
+               res= intbv(None,_nrbits=i-j)
+           else:
+                res = intbv((self._val & (1L << i)-1) >> j,
_nrbits=i-j)
             return res
         else:
             raise TypeError("intbv item/slice indices should be
integers")
############ CUT ME ###############################################


############ CUT ME ###############################################
#  _convert.py.patch
############ CUT ME ###############################################
jmatos - ~/work/hdl/myhdl-0.4.1/myhdl $ diff -u
_toVerilog/_convert.py /usr/lib/python2.3/site-packages/myhdl/_toVerilog/_convert.py
--- _toVerilog/_convert.py      2004-12-24 13:35:02.000000000 +0000
+++ /usr/lib/python2.3/site-packages/myhdl/_toVerilog/_convert.py
2005-08-31 13:58:31.000000000 +0000
@@ -654,7 +654,10 @@
            node.expr.node.obj is intbv:
             c = self.getVal(node)
             self.write("%s'h" % c._nrbits)
-            self.write("%x" % c._val)
+            if c._val is not None:
+               self.write("%x" % c._val)
+           else:
+               self.write("Z") 
             return
         self.visit(node.expr)
         self.write("[")
############ CUT ME ###############################################