[myhdl-list] Tristate logic (newbie question)

[P. M. <jos...@pt...>]

hello to all.

Is any solution for the tristate question been resolved?

The first example that i make in verilog and in vhdl is to put a value
in the data bus when READ_Z and ChipSelect_Z go down and then put the
bus in high impedance when the chip is not selected. I see it work fine.
I'm happy.

I tried to generate the same hdl in myhdl. Not happy.

I would like to use myhdl, because python is on my self-learning path,
because for what i've read i believe in xp programming and i see lot of
good things comming from python people.

Can someone help me?
I could try hack the code. Has someone done that?=20

Why there is no CVS for this project?


--
Jos=E9 Pedro Matos