[myhdl-list] toVerilog dynamic top level name

[Tom D. <td...@di...>]

I was trying to develop a class to handle the details of synthesizing a 
MyHDL function. This was all fine except for one thing that I am stuck on.

To use toVerilog, you do:

topName = toVerilog(func,*args,**kwargs)

I could not get this to work with a dynamic topName. I tried the 
following and some other attempts as well.

exec('%s = toVerilog(func,*args,**kwargs)'%(name)

func, is the name of the MyHDL function to use, *args, **kwargs are the 
signal and parameter connections  to that function. name is a string 
representation of what the top level name should be.

I don't think this is a python limitation, either my error or  because 
of how toVerilog figures out the top level name.

Any ideas?

Thanks, Tom