Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

> Tom Dillon wrote:
>
>
> No, I mean that the tuple will not be mapped to something in Verilog.
> All constants from the tuple will be directly put at the appropriate
> place in the Verilog case statement, like so:
>
> # in MyHDL: theTuple = (72, 35, 9, 109 ...)
>
> // Verilog output
> ....
> always @(posedge clk) begin: RL
>     //  ROM
>     case (addr)
>         0: dout <= 72;
>         1: dout <= 35;
>         2: dout <= 9;
>         3: dout <= 194;
>         ...
>
> Is that OK?


Yes.

>
> Ok, I'll make the last one the default. I'll include the synthesis
> pragma's for now - I don't see how they can hurt and perhaps other
> tools need them.

Sounds, good. I will run it through all the tools we have to test it.

>
>> I would love to give it a try. Also if it includes the list of 
>> signals fix from the previous posting that would be very useful.
>
>
> Yes, I'll prepare a snapshot with that fix and the ROM support.


Great.


Tom