[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Tom Dillon wrote:

>>
>> Now for the details:
>>
>> It's not necessary to use an additional memL object - the code could
>> just simply refer to the defining list dataL instead. That list would
>> not be present in Verilog - all constants would be directly present
>> in the code. I assume that's Ok for the synthesis tools?
> 
> 
> This sounds like a great idea.
> 
> When you say directly present in the code, you mean in the MyHDL source, 
> correct?

No, I mean that the tuple will not be mapped to something in Verilog.
All constants from the tuple will be directly put at the appropriate
place in the Verilog case statement, like so:

# in MyHDL: theTuple = (72, 35, 9, 109 ...)

// Verilog output
....
always @(posedge clk) begin: RL
     //  ROM
     case (addr)
         0: dout <= 72;
         1: dout <= 35;
         2: dout <= 9;
         3: dout <= 194;
         ...

Is that OK?

>> About the case statement: should it have synthesis attributes like
>> parallel_case, full_case? Should there be a default fallback or
>> not? 
> 
> 
> The cases are mutually exclusive since a unique address selects each 
> one. I have have never put attribute on them and they get inferred fine.
> 
> You should only have enough cases as the length of the tuple, since if 
> your address is bigger synthesis will figure out you don't use them all 
> optimize the rom. This is important since not all roms end up in built 
> in memories, sometimes in combinatorial logic or registers.
> 
> So I would either use the default for the last one, or leave it out. 
> Leaving it out will probably produce a synthesis warning.

Ok, I'll make the last one the default. I'll include the synthesis
pragma's for now - I don't see how they can hurt and perhaps other
tools need them.

> I would love to give it a try. Also if it includes the list of signals fix from the previous posting that would be very useful.

Yes, I'll prepare a snapshot with that fix and the ROM support.

Jan

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