Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan Decaluwe wrote:

>
> I like this. It is a feature where conversion can have an additional
> productivity advantage, as as lists/tuples of constants are easier
> to create and maintain in Python than in Verilog.

Yes, we now build roms from a python script for just that reason.

>
> Now for the details:
>
> It's not necessary to use an additional memL object - the code could
> just simply refer to the defining list dataL instead. That list would
> not be present in Verilog - all constants would be directly present
> in the code. I assume that's Ok for the synthesis tools?

This sounds like a great idea.

When you say directly present in the code, you mean in the MyHDL source, 
correct?

In Verilog you would need the case statement addressed by the index and 
outputting the value from the rom on a wire that would connect to where 
it was needed.

>
> There's no need for these constants to be intbv's - plain int's
> are just fine and easier.

I think ints would be OK for the right side of the assignment in Verilog 
since it can figure out the width from the left.

>
> So in short: a tuple of ints used in an assignment in the way you
> described, would be expanded into an equivalent case statement.
>
> About the case statement: should it have synthesis attributes like
> parallel_case, full_case? Should there be a default fallback or
> not? 

The cases are mutually exclusive since a unique address selects each 
one. I have have never put attribute on them and they get inferred fine.

You should only have enough cases as the length of the tuple, since if 
your address is bigger synthesis will figure out you don't use them all 
optimize the rom. This is important since not all roms end up in built 
in memories, sometimes in combinatorial logic or registers.

So I would either use the default for the last one, or leave it out. 
Leaving it out will probably produce a synthesis warning.

>
> All the above will come without additional effort. The high-level
> assignment will be mapped to a case statement, and all context
> that surrounds it will be there as usual.


Dual port roms as well? That is great.

>
> I have an initial implementation ready along the lines above and
> I could generate a new snapshot. If there is feedback, send it
> quickly because next week I have another assignment.


I would love to give it a try. Also if it includes the list of signals 
fix from the previous posting that would be very useful.

Tom