[myhdl-list] toVerilog: Dual-Port Block RAM generations with Xilinx ISE works!

[<dan...@we...>]

Hi,

with the latest version of toVerilog I was able to implement a Dual-Port 
RAM with synchronous read (read through) with Xilinx ISE, using XST for 
synthesis.

According to the XST manual there are certain Verilog templates, if they 
are recognized by XST it will implement them in block ram.

For example, for the Dual-Port RAM with synchronous read the Verilog 
code should look like this:

----------------------------------------------------------------------
module raminfr (clk, we, a, dpra, di, spo, dpo);

   input clk;
   input we;
   input [4:0] a;
   input [4:0] dpra;
   input [3:0] di;
   output [3:0] spo;
   output [3:0] dpo;
   reg [3:0] ram [31:0];
   reg [4:0] read_a;
   reg [4:0] read_dpra;

   always @(posedge clk) begin
      if (we)
        ram[a] <= di;

      read_a <= a;
      read_dpra <= dpra;
   end

    assign spo = ram[read_a];
    assign dpo = ram[read_dpra];

endmodule
----------------------------------------------------------------------

I did the following implementation with MyHDL:

----------------------------------------------------------------------
def dp_ram_py(clk, we, addr, di, spo, dp_addr, dpo, d_width=8, a_width=2):

   memL = [Signal(intbv(0)[d_width:]) for i in range(2**a_width)]
   read_addr = Signal(intbv(0)[a_width:])
   read_dp_addr = Signal(intbv(0)[a_width:])

   def write(clk, we, addr, di, d_width=8, a_width=2):

     while 1:
       yield posedge(clk)

       if we:
         memL[int(addr)].next = di

       read_addr.next    = addr
       read_dp_addr.next = dp_addr



   def read(read_addr, spo, read_dp_addr, dpo):
     def assign():

       spo.next = memL[int(read_addr)]
       dpo.next = memL[int(read_dp_addr)]

     return always_comb(assign)

   rd = read(read_addr, spo, read_dp_addr, dpo)
   wr = write(clk, we, addr, di, d_width=8, a_width=2)

   return rd,wr
----------------------------------------------------------------------




turning that into Verilog code with toVerilog and implementing it with 
ISE, synthesis reported this:



=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dp_ram>.
     Related source file is ../../rtl/verilog/dp_ram.v.
     Found 4x8-bit dual-port block RAM for signal <memL>.
     -----------------------------------------------------------------------
| mode               | write-first                         |          |
| dual mode          | write-first                         |          |
| aspect ratio       | 4-word x 8-bit                      |          |
| clock              | connected to signal <clk>           | rise     |
| dual clock         | connected to signal <clk>           | rise     |
| write enable       | connected to signal <we>            | high     |
| address            | connected to signal <addr>          |          |
| dual address       | connected to signal <dp_addr>       |          |
| data in            | connected to signal <di>            |          |
| data out           | connected to signal <spo>           |          |
| dual data out      | connected to signal <dpo>           |          |
| ram_style          | Auto                                |          |
-----------------------------------------------------------------------
     Summary:
         inferred   1 RAM(s).
Unit <dp_ram> synthesized.



Cheers,

Guenter