[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> 
>>
>>   memL = [Signal(intbv(...)) for i in range(depth)]
>>
>>   def wrLogic() :
>>       while 1:
>>       yield posedge(clk)
>>       if we:
>>           memL[int(wr_addr)].next = din
>>
>>   def rdLogic() :
>>     while 1:
>>       yield posedge(clk)
>>       dout.next = memL[int(rd_addr)]
> 
> 
> 
> In this example I could use rd_clk and wr_clk instead of clk twice?

Definitely.

> That looks very good, and I now better understand intbv vs. Signal. So 
> by definition, an intbv is a  variable and Signal is a signal.

Yes, but be careful to put them against each other like that. intbv
is just one of the variable types that toVerilog can handle, others
are int, bool, and enum. Likewise, toVerilog can handle Signals
constructed from a number of base types.

See also the manual 6.4.3: Supported types. It may also be a good
idea to take a fresh look at the examples in 6.6. Especially enum
usage in 6.6.4 should be of interest to FPGA designers.

 > I started
> out thinking I could only use Signals if going through toVerilog.

Certainly not. What happens is that variables and Signals should be
used as in VHDL, and that variable assignment is mapped to blocking
assignment, and signal assignment to non-blocking assignment.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html