Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan,


>>  memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]
>
>
> Note that .min and .max are supported attributes of intbv's and
> Signals - no need to use the private attributes. (This should never
> be required - if there seems a need for it, let me know.)

Thanks.

>
>   memL = [Signal(intbv(...)) for i in range(depth)]
>
>   def wrLogic() :
>       while 1:
>       yield posedge(clk)
>       if we:
>           memL[int(wr_addr)].next = din
>
>   def rdLogic() :
>     while 1:
>       yield posedge(clk)
>       dout.next = memL[int(rd_addr)]


In this example I could use rd_clk and wr_clk instead of clk twice?

That looks very good, and I now better understand intbv vs. Signal. So 
by definition, an intbv is a  variable and Signal is a signal. I started 
out thinking I could only use Signals if going through toVerilog.

Tom