Re: [myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> How difficult to add the capability to handle the following?

See below for some qualifications to your proposal first and
if you agree.

I would like to come up with a general solution for RAM support,
also including a way to convert to assign statements for
simple combinatorial blocks, as discussed in other posts.

I'm working on this currently and I think it should be possible
to release something early next week.

>  memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]

Note that .min and .max are supported attributes of intbv's and
Signals - no need to use the private attributes. (This should never
be required - if there seems a need for it, let me know.)

>    def wrLogic() :
>    while 1:
>      yield posedge(clk)
>      if we:
>        memL[int(wr_addr)][:] = din
> 
>  def rdLogic() :
>    while 1:
>      yield posedge(clk)
>      dout.next = memL[int(rd_addr)]
> 
>  WL = wrLogic()
>  RL = rdLogic()
>  return WL,RL
> 
> This would allow true dual port capability like most FPGAs now have.
> 
> I overlooked this in my initial posting. Also may want a rd_clk and wr_clk.

That is no problem - clocks will be as defined in the sourcecode.

> You would need to pull the reg definition out of the process and give a 
> unique name to it.

Exactly - like for signals. The logic of MyHDL (similar to VHDL) is
to use a list of Signals in this case: signals are used for
communication between generators, variables internally. So the
code would look like:

   memL = [Signal(intbv(...)) for i in range(depth)]

   def wrLogic() :
       while 1:
       yield posedge(clk)
       if we:
           memL[int(wr_addr)].next = din

   def rdLogic() :
     while 1:
       yield posedge(clk)
       dout.next = memL[int(rd_addr)]

> If I do this now, it generates everything correct but leaves out the reg 
> define.

That qualifies as a bug - it should give an error. (The principle is:
if the MyHDL simulation works and the conversion succeeds, the converted
code should be correct.)

I noticed that this was bug was present for non-list types also and
I have already added code to my development version that flags this
situation as a conversion error.

Jan

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