[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:
> Jan,
> 
> I tried a simple example with the memory and to implement it with ISE
> 6.3, but ran into some problems. I am not sure whether I did something
> wrong how I wrote the MyHDL code or need to do some special ISE
> settings? I basically pulled in the generated Verilog file into a ISE
> project with the standard settings and ran it through implementation.

I don´t have ISE installed - I rely on external feedback for this.
So feedback on specific tool experiences is very welcome.

> Here is the MyHDL code that I used:
> 
> 
> def ram(clk, dout, din, addr, we, d_width=8, depth=4) :
> 
>   memL = [intbv(0)[d_width:] for i in range(depth)]
> 
>   while 1:
>     yield posedge(clk)
> 
>     if we:
>       memL[int(addr.val)][:] = din.val
> 
>     dout.next = memL[int(addr.val)]
> 
> 
> 
> 
> and that is the generated Verilog code:
> 
> 
> module inst_ram (
>     clk,
>     dout,
>     din,
>     addr,
>     we
> );
> 
> input [0:0] clk;
> output [7:0] dout;
> reg [7:0] dout;
> input [7:0] din;
> input [1:0] addr;
> input we;
> 
> 
> 
> always @(posedge clk) begin: _MYHDL1_BLOCK
>     reg [8-1:0] memL [0:4-1];
>     if (we) begin
>         memL[addr] = din;
>     end
>     dout <= memL[addr];
> end
> 
> endmodule
> 
> 
> The first thing ISE tripped over was that the memL array is inside the
> always statement. Moving it out from there made it go on, but then there
> is a blocking and nonblocking assignment inside the always statement and
> that one it did not like either.

The latter part is really stupid. I know where this comes from, and I
know this rule is in the mainstream, but that doesn´t make it less
stupid. Tool developers should be wiser.

> Is it possible to change that with the toVerilog conversion?

I cannot change the fact that using both signals and variables in
a generator (= blocking and nonblocking in an always block) is
an essential part of HDL design.

However, for simple cases, there are workarounds, such as breaking
an always block into several ones. This could be done (in the input
MyHDL code) in this specific case of ram inference.

To make that work, what is missing in toVerilog is the capability to
define the memory outside of a generator, as reported by others also.
I´m currently thinking about a solution.

> I also recognized that the 'clk' signal is specified as input [0:0]
> whereas the 'we' signal is specified only as input.

Probably this is because clk is defined as an intbv instead of a bool.

Jan

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