Re: [myhdl-list] Re: syntax sugar?

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> On 8/1/05, Jan Decaluwe <ja...@ja...> wrote:
> Jan,
> I generally agree with your comments against "syntax sugar" so I won't
> argue about it. Also thanks for pointing out a less verbose way to
> keep track.
> 
> On the following point I want to point out a drawback:
> when you group all assignments you are making all the assignments
> sensitive to all signals on the RHS, and therefore whenever an event
> happens every single assignment will be evaluated. That may or may not
> be acceptable in terms of simulation efficiency, but it is not
> equivalent to multiple concurrent assignment blocks. Or maybe I don't
> understand what instances() and always_comb() do?

With the current implementation, you are correct. However, this could
be optimized. This is similar to the current discussion in another
thread about conversion to Verilog assign statements.

always_comb() inspects the function source code to infer a sensitivity
list. It returns a single generator. It could be enhanced to detect
the case in which the function only contains assignments (no control
logic or declarations). In that case it could infer a sensitivity
list and return a generator per individual assignment.

Jan

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