Re: [myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

(I think something went wrong with gmane yesterday, and the following
message from Tom Dillon didn=B4t show up in gmane. So I repost it
-- Jan Decaluwe)

Tom Dillon wrote:
> Jan,
>=20
> How difficult to add the capability to handle the following?
>=20
>  memL =3D [intbv(0,min=3Ddout._min,max=3Ddout._max) for i in range(dept=
h)]
>    def wrLogic() :
>    while 1:
>      yield posedge(clk)
>      if we:
>        memL[int(wr_addr)][:] =3D din
>=20
>  def rdLogic() :
>    while 1:
>      yield posedge(clk)
>      dout.next =3D memL[int(rd_addr)]
>=20
>  WL =3D wrLogic()
>  RL =3D rdLogic()
>  return WL,RL
>=20
> This would allow true dual port capability like most FPGAs now have.
>=20
> I overlooked this in my initial posting. Also may want a rd_clk and wr_=
clk.
>=20
> You would need to pull the reg definition out of the process and give a=
=20
> unique name to it.
>=20
> If I do this now, it generates everything correct but leaves out the re=
g=20
> define.
>=20
> Tom
>=20
>=20
> Jan Decaluwe wrote:
>=20
>> Tom Dillon wrote:
>>
>>> Jan,
>>>
>>> That works great, I use it with the following code:
>>>
>>>  memL =3D [intbv(0,min=3Ddout._min,max=3Ddout._max) for i in range(de=
pth)]
>>>    while 1:
>>>        yield posedge(clk)
>>>        if we:
>>>          memL[int(addr)][:] =3D din
>>>          # print "ram: wrote %d to %d"%(din,addr)
>>>        dout.next =3D memL[int(addr)]
>>>
>>> This synthesized into Virtex blockRAM using Mentor Precision just fin=
e.
>>
>>
>>
>> Ok. The code was committed to the next release.
>>
>=20
>=20
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>=20


--=20
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html