Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan,

How difficult to add the capability to handle the following?

  memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]
   
  def wrLogic() :
    while 1:
      yield posedge(clk)
      if we:
        memL[int(wr_addr)][:] = din

  def rdLogic() :
    while 1:
      yield posedge(clk)
      dout.next = memL[int(rd_addr)]

  WL = wrLogic()
  RL = rdLogic()
  return WL,RL

This would allow true dual port capability like most FPGAs now have.

I overlooked this in my initial posting. Also may want a rd_clk and wr_clk.

You would need to pull the reg definition out of the process and give a 
unique name to it.

If I do this now, it generates everything correct but leaves out the reg 
define.

Tom


Jan Decaluwe wrote:

> Tom Dillon wrote:
>
>> Jan,
>>
>> That works great, I use it with the following code:
>>
>>  memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]
>>    while 1:
>>        yield posedge(clk)
>>        if we:
>>          memL[int(addr)][:] = din
>>          # print "ram: wrote %d to %d"%(din,addr)
>>        dout.next = memL[int(addr)]
>>
>> This synthesized into Virtex blockRAM using Mentor Precision just fine.
>
>
> Ok. The code was committed to the next release.
>