[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Günter Dannoritzer wrote:

> My show stopper was that I did not really know how to implement the
> assign statement. I searched through the mailing list archive and found
> a post from March 2nd of this year with the subject "syntax sugar?" from
> Haitao Zhang.

I just posted a delayed answer to that post. Note that what Haitao
asked for was MyHDL assign statements equivalent to Verilog. It is
not immediately clear how to do that, but I think the MyHDL alternative
is not that bad. See my answer there.

What you ask for is assigns in generated Verilog. They are used already
to implement constant value assignments. I think their usage could be
extended to keep Xilinx tools happy without jeopardizing generality.
A possible solution is as follows. It should be possible to detect
simple always_comb blocks: those that consist of assignments only
(no declarations or control logic.) Instead of converting them
to an always block, they could be converted to a series of assigns
statements.

Regards,

Jan

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